Modeling of Leakage Current Mechanisms in Nanoscale DG MOSFET and its Application to Low Power SRAM Design

Double-Gate (DG) MOSFET has emerged as one of the most promising devices for logic and memory circuit design in sub 10nm regime. In this paper, we investigate the gate-to-channel leakage, EDT, BTBT and sub-threshold leakage for DG MOSFET. Simulations are performed using 2D Poisson-Schrödinger simulator with tight-binding Green’s function approach. Then we analyze the effect of parameter variation to optimize low leakage SRAM cell using DG devices. The DG device/circuit co-design successfully demonstrates the benefit of using metal gate intrinsic body DG devices which significantly reduces BTBT and EDT in SRAM architecture.